1. Field of the Invention
The invention relates to an improved method for fabricating metal semiconductor field effect transistor (MESFET) devices, and, in particular, a method for fabricating a self-aligned gate MESFET wherein the separation between the gate electrode and the dopant self-aligned contact is controlled to optimize the parasitic source resistance to gate capacitance ratio thus improving device performance.
2. Description of the Prior Art
Factors which have limited the performance and yields obtainable in conventional FET processing techniques are the need to perform either (1) a precise recess etch to reduce the FET pinch-off voltage, or (2) a critical realignment of the gate electrode to an existing active channel region to reduce source resistance. A prior art technique solution to these problems is disclosed in the articles "A Self-Aligned Source/Drain Planar Device for Ultrahigh-Speed GaAs MESFET VLSIs" by N. Yokoyama, et al., ISSCC Digest of Technical Papers, pp. 218-219 (February 1981), and "Ti/W Silicide Gate Technology for Self-Aligned GaAs MESFET VLSI's" by Yokoyama, et al., International Electron Device Meeting Proceeding, pp. 80 (1981). In particular, a fabrication process is described wherein an active channel layer is formed on a semi-insulating substrate and a refractory metal gate is used as a self-aligned mask for an implant which established the n.sup.+ contact regions. In this instance, the MESFET Pinch off voltage is controlled by the channel implant (no recess etch is required) and the source parasitic resistance is reduced by the self-aligned n.sup.+ contact implant.
A critical factor in using self-aligned gate techniques is the proximity of the n.sup.+ regions to the gate. A tradeoff exists between parasitic source-gate resistance and parasitic gate capacitance as the proximity of the n.sup.+ contact close to the gate lowers the parasitic resistance (as discussed in Yokoyama et al. articles) but raises the gate capacitance and vice versa. Further, the position of the n.sup.+ regions with respect to the gate also influences the breakdown voltage of the gate contact to semiconductor Schottky barrier.
The process described in the Yokoyama et al. references approaches the tradeoff problem by varying the depth of the buried n.sup.+ implant relative to the channel implant. A problem with this approach is the relatively high resistivity layer between the ohmic contact and the peak of the n.sup.+ implant, a problem inherent in the use of a buried implant where a current path to the surface must exist. This reduces device switching speeds, increases power requirements in digital circuits and increases the noise factor while lowering the frequency response when the device is utilized in analog circuits.